Without limiting the scope of the disclosed embodiments, various semiconductor, circuit, and integrated circuit (“IC”) devices, such as system-on-chip (“SoC”) devices, are emulated or verified during their design and development processes. As an example, highly-integrated SoC devices may power or support a wide variety of products to allow various hardware, software, and/or device applications. To meet these demands, SoC devices continue to increase in size and complexity, and their capabilities and manufacturability are in part aided by advance semiconductor processing technologies and availabilities of verified or well-developed libraries, e.g. design or circuit intellectual property (“IP”) libraries. The development of SoCs or other circuits or device in some cases nevertheless may increase the burdens on design verification processes, methods, or systems. In some cases, verification may consume a significant amount of time or resources during an SoC development cycle.
Circuit design verification approaches can vary. Given the expectation for speed, the various approaches of software development, hardware development, or system validation may provide varying levels of observability and control. Field programmable gate array (“FPGA”) prototype systems, for example, can provide improved system execution time due to its hardware-based nature. Some FPGA verification systems, nevertheless, may lack the ability to isolate some of the root causes of discoverable errors for various reasons, such as due to the lack of visibility regarding certain signal values within the design. Depending on the environment, software, and hardware constraints in some cases, deficiencies in certain FPGA vendor-specific verification tools may include access to a limited number of signals, and limited sample capture depth. Even combined with an external logic analyzer, FPGA vendor-specific verification tools, in some instances, may lack sufficient capabilities to isolate root cause errors during design verification. Also, FPGA vendor-specific verification tools typically only work with their own FPGA device types and typically cannot be customized to other FPGA type devices.
It therefore may be desirable to have methods or apparatus that can meet the design verification demands of highly-integrated SoC or other circuit or IC devices in certain applications or can provide design verification systems having improved control and/or observability of signals on FPGA-based electronic prototype systems. Also, it may be desirable to have a capability of advanced debugging on customized prototype systems such that a design or SoC verification flow can be applied for various types of FPGA devices.